Wilder Technologies SATA 2.5 Test Adapter Manual de usuario

数据中心的最新高速工业总线测试及SI仿真技术 Chang Yufei 2014.4

Testing Challenges in Tx  Meet the requirements for effective testing √ Compliance mode support, proper patterns and toggling mechanism √ Correct Tx

Introducing the NEW Opt PCE3  TekExpress Automation for Tx Compliance with unique features including: √ Sets up the Scope and DUT for testing √ Toggl

What’s New in Option PCE3 Release 2?  Supports a faster, Python-based sequencer – Much faster program launch with the test time reduced by ~50% – 64-

Automation Simplifies Tx Testing  While convenient single capture capability is essential, automation makes the testing practical  Iterate over mult

Automated DUT Control Ref Clk Data System Board / Mother Board with Multiple Slots CLB with toggle switch Oscilloscope AFG or AWG Control 100MHz B

Add-In Card Test Fixture  Compliance Base Board (CBB) – Used for Testing Add-In cards – All Tx / Rx Lanes are routed to SMP – Compliance Mode Toggle

System Test Fixtures  Compliance Load Board (CLB) – Used for testing System Boards – All Tx / Rx Lanes and Ref Clk routed to SMP – Compliance Mode To

TekExpress Automation for Tx Compliance - Setup Run Analysis on Live or Pre-Recorded Data Type of test / device selection Test selection Automate DUT

TekExpress Automation for Tx Compliance – Test 18 Test Selection

TekExpress Automation for Tx Compliance – Reports

High-Speed Serial Test Trends and Implications • 100 GbE is becoming more relevant as data centers and communications networks ask for more bandwidth

PCIe Decoder (Opt SR-PCIe)  Decodes and displays PCIe data using characters and names that are familiar from the standard, such as: – SKP – Electrica

PCIe Decoder (Opt SR-PCIe) Decoding of PCIe Gen3 compliance pattern Tx preset encoding  xxx Decode results show correct value of “87h” or “1000b” (as

RF Switch and Auto Toggling  Use RF switch to handle multiple lanes without reconnections √ Must provide termination to maintain compliance mode √ Us

PCI Express Tx Test with RF Switch

Cable and RF Switch De-embed

Comparison of De-embedding: System System Board (P7) With de-embed Without de-embed Diff SigTest Measurement Switch & extra cable effects remov

Testing Beyond Compliance  What happens if a measurement fails Compliance ?  Could it be the channel? – Measurements can be taken before the channel

PCIe Gen3 Rx Solution 27

Essentials of Rx Testing  PCIe 3.0 introduced formal Rx testing  Based on stress testing of the DUT in loopback – Looped back data must be the same

Basic Receiver Testing At the simplest level, receiver testing is composed of: 1. Send impaired signal to the receiver under test 2. The receiver de

High-Speed Serial Test Trends and Implications • 100 GbE is becoming more relevant as data centers and communications networks ask for more bandwidth

Stress Composition Tx Eq 8G PRBS Gen RJ Source SJ Source Combiner Diff Interference Cal. Channel Test Equipment CM Interference Post-processing Eye He

Components of a PCIe3 Receiver Test Solution  BERTScope C Model – PG, stressed eye sources, ED  New! DPP125C Option ECM – Eye opener, Clock doubler/

DPP125C with Option ECM  Integrated reference clock multiplication to PCIe compliant 2.5 GHz, 5 GHz, and 8 GHz.  Integrated eye opener functionality

BSAITS125 Interference Test Set  Programmable, variable ISI for automated testing and precision setting  Built-in compliant PCIe2 and PCIe3 Medium a

Typical PCIe3 Rx Test Configuration

BSAPCI3 PCIe 3.0 Automation SW • Automated calibration, link training, loopback initiation, and testing. • BER Map feature for TxEQ optimization. • Re

Automated Link Equalization  Loopback results: automation software provides complete equalization request log  DUT 2 requests only one equalization

Automatic Calibration  Due to complex test setup and variations in DUTs and test equipment just dialing up the settings on the signal source is not s

Stressed Eye Calibration Setup • Three required calibrations are fully automated • Detailed cabling diagrams are provided for each calibration step

Add-In Card: Receiver Stressed Eye Testing

PCIe Gen3 Tx 4

Host (System): Receiver Stressed Eye Testing

Rx Testing Summary  Certainly the most complex type of testing – Due to complexity of equipment and procedures  Extensive correlation studies in PCI

Beyond Compliance: BERTScope Analysis Tools  Besides being a BERT, the BERTScope’s “Scope” functionality brings benefits that complement those of the

PCIe Gen3 Protocol

PCI Express Protocol Test Solution  8, 5, 2.5 GTs  x8 & x4  8 State Triggering  8 GB memory – 16 GB for x16  OpenEYE  FastSYNC  Module setu

 Automatic display of Transaction Window with Listing Window  Errors with timestamps and link direction  Expanded Training sets with all of the TS

Gen4 Update • Key attributes/requirements of PCIe 4.0 o 16 GT/s, using scrambling, same as 8 GT/s, no encoding change o Maintains compatibility w/ PCI

Gen4 Update  Tx Jitter – Analysis solution available today with PCE3.  Tx EQ – CEM and Embedded will have limited change. Base might require Samplin

SATA and SAS Industry Timeline Today 2010 2011 6G Deployment Phase – Commercial Gen3 product deployment. – Commercial product deployment. Gen 4 (24 G

SATA3 Tx & Rx Solution

Testing Challenges with PCI Express 3.0 Physical Layer Data Link Layer Transaction Layer PCIe Core HW/SW Interface Device Core Physical Layer Data Lin

Embedded Applications SATA BGA Today, SATA is expanding in specialized low power, compact and high performance areas with BGA, small form factor, dire

NEW SATA 3.2 Specification  SATA Express: – Includes both SATA and PCIe signaling – Hosts supports both SATA or PCIe storage device. – With PCIe t

What’s new with SATA testing?  UHost: A SATA host that provides for attachment of a Gen1i/Gen2i/Gen3i endpoint device directly to the mating connecti

SATA Transmitter Tests PHY TSG OOB

Transmitter Test Patterns  HFTP (High Frequency Test Pattern) 0101010101 0101010101 D10.2 D10.2  MFTP (Mid Frequency Test Pattern) 00

Test Pattern Generation  BIST-TSA: Self generated transmission of pattern (required) – T: Transmit only (no Rx required) – S: Scramble Bypass – A: AL

AWG Device State Control  DUT control a significant challenge  BIST-L (loopback) required for compliance  AWG has a successful track record of DUT

‘Direct Attach’ Usage Models  Formally referenced as M.2, USM, or MicroSSD  Devices meet Gen1i/2i/3i specifications  Hosts meet Gen1u/2u/3u specif

SATA PHY Test Solution  TekExpress SATA-TSG software  NEW TekExpress version in Q2 (M.2, mSATA, etc.)  AWG BIST-L library  Updated periodically, f

SAS3 -- Challenge to 12Gbps 59

PCIe Base vs CEM Testing  What test point each type of testing addresses?  How do we get to see the signal at the point of interest? Capture Measu

12G+ Design Problem: 1000mV, FFE, Crosstalk, DFE, 50mV  Crosstalk and signal loss problems are the largest design challenge today.  Significant ad

Measurement for Crosstalk/ISI Evaluation  SAS3_EYEOPENING* Measurement for accurate analysis of ISI and crosstalk effects  Provides measure of rela

SAS3_EYEOPENING provides 4 different metrics 1. Relative Vertical Eye Opening: A direct indication of how much margin there is after equalization – Ta

A Note about SAS Test Points IT ER ET IR

SAS-3 PHY Transmitter Solution SAS-3 1.5/3/6/12 Gb/s Tx Test Software TekExpress SAS3-TSG Automation Software Group 1 – OOB Signaling 5.1.1 Maximum

SAS-3 PHY Transmitter Solution Option SAS3-TSG  Automated transmitter validation for 1.5, 3, 6 and 12 Gb/s SAS physical layer specification  Integ

Beyond Compliance  How much margin is there in my design?  How many DFE/FFE taps are needed to meet the system budget?  What is longest channel (ca

Flexible Link Analysis Tools  DFE/FFE modeling – Reference equalizer vs. vendor-specific (IBIS-AMI) – Equalization key differentiator for PHY vendors

Recommended Equipment The following components are required for performing SAS12 Tx measurements DPO/MSO70000C/D/DX Series Oscilloscope with Opt. 2X

SAS 12 Gb/s Rx Test Setup  Similar to SAS 6 Gb/s Rx configuration  Rx calibration -> CJTPAT -> BER test  Tektronix Method of Implementation (

 Base Specification Measurements are defined at the pins of the transmitter  Signal access at the pins is often not possible  De-embedding is requi

SAS 12G Rx Equipment DUT Crosstalk 2X Test Adapter ISI RX TX

Trained Link for Jitter Tolerance Test  Complete Rx test exercises both CDR and Tx/Rx EQ capabilities  Current options for training link – Iterate p

Stressed Pattern Calibration – Putting it Together Stressed Pattern Generator Link Training BERTScope DPP125 Pre-Emphasis Channel (crosstalk/ISI

Rx Results (BERTScope) DATA T-MHz T-SJ SJ Bits Errors BER Status ThreshVX DelayPS 2 0.1 4.52 6E+08 0 0.00E+00 PASSED 0 267.531 4 0.1

USB3 – from 5Gpbs to 10Gbps 74

Increasing Serial Data Bandwidth  USB 2.0, 480 Mb/s (2000) – Shift from slower, wide, parallel buses to narrow, high speed serial bus – 40x faster da

Interoperability Challenge  Goal: Any certified host works with any certified hub or device  Short Channel – 1" host PCB route – ¼ " devi

Why USB 3.1 is more challenging Gen1 Gen2 Data Rate 5 Gb/s 10 Gb/s Encoding 8b/10b 128b/132b Target Channel 3m + Host/Device channels (-17dB, 2.5

USB 3.1 Transmitter Measurement Overview Clock (CP10) PHY (CP9)* LFPS Spec Reference Parameter Table 6-16 SSC Modulation Rate SSC Deviation Table 6

Example Host Test Setup SMA cable to scope Host Short USB cable Ping.LFPS from signal generator (pattern toggle)

Add-In Card (CEM Spec) Tx Testing  CEM Specification Measurements are defined at the slicer of a receiver  Signal access is not possible  Embedding

SDLA is critical for USB 3.1  Find optimum Eye height vs. Rx EQ 60 mV - Fail 103 mV - Pass 63 mV - Fail

USB 3.1 Recommended Transmitter Solution  ≥ 20 GHz BW, 100 GS/sec preferred  >10M minimum record length allows capture of 1M UI at 100 GS/sec, n

Receiver Testing  Jitter Tolerance (JTOL) with swept jitter profile, reference channel – Verify CDR tracking and ISI compensation  Link optimization

BERTScope USB 3.0 RX Test Configuration USB Switch* creates the low-frequency periodic signaling (LFPS) required to initiate Loopback-mode DPP125C D

SDLA – Embed / De-Embed Simulation / Equalization 84

Why use Link Analysis Applications?  Maximize Margins Compensate for margin loss due to test fixtures, cables, probes or other artifacts of the me

Open Closed Eyes Apply Receiver Equalization  In the past, acquired signals could be measured directly, even at the far end – Increasing data rates r

Remove Reflections Virtual Probing at Ideal Test Point  Reflections may be present when probing at non-ideal locations, which are not present at the

Tektronix HDMI 2.0 Solution  DPO/DSA/MSO 70004B/C/D/DX Series Real Time Oscilloscope with BW ≥ 16GHz ( we also support 12.5GHz BW scope for HDMI 2.0

Tektronix MHL Solution: Complete Solution for Phase 1 CTS 3.0 needs  Tektronix MHL Physical Layer Tx test setups are easy to use and automated ( OPT

Compliance Patterns  Once in compliance mode, bursts of 100MHz clock can used to cycle through various settings of compliance patterns to perform,

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