Wilder Technologies SATA 2.5 Test Adapter Manual de usuario

高速串行测试方案介绍 泰克华南区技术支持工程师 余岚

Desktop Cables Concept PCIe Cable Existing SATA Cable PCIe Cable PCB PCB PCIe/SATA Conn. PCIe Conn.  SATA devices will coexist with next generation P

SATA Express Signal Access  Recommend Luxshare-ICT Dual Port SAS fixtures (SFF-8482)  Similar dimensions but different pinout  For device testing

Tektronix Solutions for SATA Express Measurements  DPOJET-based SATA Express setup (requires option PCE3)  Support for Base/CEM spec measurements 

12G+ Design Problem: 1000mV, FFE, Crosstalk, DFE, 50mV  Crosstalk and signal loss problems are the largest design challenge today.  Significant ad

SAS-3 PHY Transmitter Solution SAS-3 1.5/3/6/12 Gb/s Tx Test Software TekExpress SAS3-TSG Automation Software Group 1 – OOB Signaling 5.1.1 Maximum

NEW Measurement for Crosstalk/ISI Evaluation  SAS3_EYEOPENING* Measurement for accurate analysis of ISI and crosstalk effects  Provides measure of

SAS Receptacle Test Adapter Sdd21 (1x Thru) => -3dB@26 GHz

Test Fixture De-embedding  Why de-embed? – Tx measurements referenced to die (ET) – Improve margin with removal of fixture effects  S-Parameters acq

Mini-SAS HD Plug Test Adapters High-Performance Mini-SAS HD Plug Connector Configuration 16 SMAs for High-Speed Testing 8 Position Low-Spee

Bandwidth Considerations SAS 12G NRZ Power Spectrum

2013/11/6 2 High-Speed Serial Data Test Solutions Design Verification Compliance Test Interconnect Test Interconnect Tx + - + - + - + - Rx Transmitt

12G PRBS from BERT (20ps 20-80% Tr) 03/21/2012- Tektronix Confidential 20 18 GHz (3rd harmonic) 24 GHz (4th harmonic) 33 GHz (~5th harmonic)

Recommended Equipment The following components are required for performing SAS12 Tx measurements  DPO/MSO70K(C/D) Series Oscilloscope with Opt. 2XL

Thunderbolt Overview  High Speed Data Bus for PC’s – Brought to market by Intel/Apple in 2011 – Interoperable with DisplayPort  Thunderbolt signalin

 All measurements are near end with Fixtures fully de-embed.  Requires DisplayPort 1.2 conformance testing  Source Test Suite  PHY1.1 – Transitio

Thunderbolt Transmitter Testing Fully supported in Tektronix’s current solutions 24

Thunderbolt Test Connectivity 4 High Speed Thunderbolt Diff Pairs 8 Low Speed Signal lines for Control and Power Testing (10 – Position Connector) Th

11/6/2013 10GBASE-T - Overview  10GBASE-T provides 10 gigabit/second connections over unshielded or shielded twisted pair cables, over distances up t

2013/11/6 XGbT – 10GBASE-T 发送端测试

2013/11/6 Transmitter Power Spectral Density (PSD) and Power Level 发送端功率谱密度及功率值  目的 : 确保发送端功率谱密度和功率值满足规范要求。  功率值应在3.2dBm~5.2dBm范围内 功率谱密度曲线应介于

11/6/2013 TF-XGbT Test Fixture  The XGbT test fixture provides easy access to the 10GBASE-T Electrical signals to perform conformance testing and dev

Storage Timelines and Solutions Development Today 2008 2009 2010 2011 Gen 3- Silicon Phase 6G Integration Phase – Product Development – SATA IO Uni

10G-KR Typical Backplane Ethernet 11/6/2013 30

10G-KR自动化测试软件 June 5, 2012 Tektronix Confidential 31

Testing connection for 10G-KR June 5, 2012 Tektronix Confidential 32

10Gigabit Ethernet Interface Evolution Next Big Thing SFF-8431 SFP+ Source : Ethernet Alliance 11/6/2013 33 QSFP

Tektronix SFP-TX – Automation & DPOJET Option 11/6/2013 34

SFP test connection 11/6/2013 35

SFP Eye Mask hit ratio :less than 5E10-5 11/6/2013 36

Add-In Card (CEM Spec) Tx Testing  CEM Specification Measurements are defined at the slicer of a receiver  Signal access is not possible  Embedding

Compliance Patterns  Once in compliance mode, bursts of 100MHz clock can used to cycle through various settings of compliance patterns to perform,

PCIE Dual-Port TX Measurement Example for System PCI Express* 3.0 Compliance Data 100 MHz Reference Clock All other lanes are terminated with 50 Ohm

SATA UTD 1.4 TSG/PHY/OOB Measurements  PHY TRANSMITTED SIGNAL GROUP REQUIREMENTS (TSG 1-12)  Different test program and degrees of regress

Automated DUT Control 16-JUL-2013 40 Ref Clk Data System Board / Mother Board with Multiple Slots CLB with toggle switch Oscilloscope AFG or AWG Co

TekExpress Automation for Tx Compliance - Setup 41 Run Analysis on Live or Pre-Recorded Data Type of test / device selection Test selection Automate D

TekExpress Automation for Tx Compliance – Test 42 Test Selection 16-JUL-2013

TekExpress Automation for Tx Compliance – Reports 43 16-JUL-2013

TekExpress Automation for Tx Compliance – Reports 44 16-JUL-2013

Basic Receiver Testing 16-JUL-2013 45 At the simplest level, receiver testing is composed of: 1. Send impaired signal to the receiver under test 2.

June 5, 2012 Tektronix Confidential 46 RX Measurement Example for Host

USB 3.0 Key Considerations  Receiver Testing Now Required – Jitter tolerance – SSC, Asynchronous Ref Clocks can lead to interoperability issues  Cha

USB 3.0 Compliance Test Configuration  USB 3.0 is a closed eye specification – Reference channel is embedded and CTLE is applied  USB 3.0 Reference

USB 3.0 Transmitter Measurement Overview  Voltage and Timing – Eye Height – Pk to Pk Differential Voltage – RJ – DJ – TJ – Slew Rate  Low Frequency

SATA/SAS Physical Layer Validation 5 SATA/SAS TSB/PHY/OOB 5

Complete USB 3.0 Transmitter Solution DPO/DSA70000 Series Oscilloscopes  Go Beyond Compliance Testing – Debug Suite with DPOJET – SDLA for Channel Mo

Increasing Serial Data Bandwidth  USB 2.0, 480 Mb/s (2000) – Shift from slower, wide, parallel buses to narrow, high speed serial bus – 40x faster da

Transmitter Validation Example - DPOJET  Recall DPOJET SSP setups

HDMI Basics 53 AEU 2013 Sol 311-309 HDMI MHL Test Solutions

54 HDMI 测试方案-源端 EFF – HDMI –TPA - P P7313SMA Or EDID board 03.30 ET – HDMI –TPA - P

55 HDMI Source Testing Source Sink Cable – Rise/Fall Time – Inter-pair Skew – Clock Duty Cycle – Clock Jitter – Eye Diagram – Voltage VL – Intra-pair

56 HDMI Sink Testing Source Sink Cable – Jitter Tolerance – Min/Max Differential Swing – Intra-Pair Skew – Differential Impedance

HDMI LLC Seminar 2013/11/6 57 AWG7122B/C AWG7122B/C Efficere TPA-P Sink DUT D0 Clock D1 D2 Bias Tee Bias Tee Bias Tee Bias Tee Bias Tee Bias Tee Bia

HDMI LLC Seminar 2013/11/6 58 HDMI 1.4 HEAC Solution Configuration Tx Test Setup Rx Test Setup

Tektronix HDMI 1.4a Test Solutions HEAC Fixtures 174-5834-00

June 5, 2012 Tektronix Confidential 6 SATA/SAS TSG/PHY/OOB test connection

HDMI LLC Seminar 2013/11/6 60 Tektronix HDMI 1.4a Test Solutions HEAC Software

Proposed HDMI 2.0 features-Not finalized  Uses same Cat 2 Cable and HDMI 1.4b connector  Support 4K 2K 4:4:4 60 Hz – 594Mhz  Support 4K 2K 4:2:0

Rise time Needs • HDMI 1.4b, should be capable of measuring 75 psec, but no word about the System Rise time. • HDMI 2.0 should be capable of mea

What is the system bandwidth needed to measure 42.5 (20-80% )psec or less DUT Rise time  System bandwidth should be around (42.5/1.5 ) 28psec  S

Conclusion  16GHz BW scope will give 1% error and hence is recommended for HDMI 2.0 testing.  HDMI 2.0 RT/FT (20%-80%) data signals is 42.5ps 64

HDMI 2.0 Source Testing-Advanced information

Source Testing 1.4b Vs 2.0 Eye Diagram test is changed Rest of the tests is same 1.4b CTS test is a pre-requsite for HDMI 2.0 Min 8GHz scope to 16G

Likely Source Electrical tests Test ID HF1-1: Source TMDS Electrical – 340-600Mcsc – VL Test ID HF1-2: Source TMDS Electrical – 340-600Mcsc – TRISE, T

Source Eye Diagram Test SMA Pair Cable HDMI Source Clk + Clk - Tektronix Oscilloscope DPO/DSA/MSO70000 Series ≧ 16GHz Include Reference Cable Emulator

TP2 Source Eye for HDMI 2.0 6G signal Single End Input eye rendered at Tek lab TIF - Validating Next Generation Display Interfaces

SATA/SAS Physical Layer Validation SATA/SAS: test Report

HDMI 2.0 Tx Compliance Software

Tektronix HDMI Protocol Analyzer

MHL Introduction MHL Customer Presentation  Mobile HD Link (MHL) technology is a low pin count HD audio and video interface that connects portable e

MHL Introduction Source: MHL 1.2 specification document  MHL Consortium was formed in Sept 2009 with the following founding members: - NOKIA - SAMSU

Tektronix MHL 2.1 Tx Solution with Direct Attach test support MHL Customer Presentation

Tektronix MHL Tx Setup MHL Differential and CM Test Setup 7 tests Single Ended and Intra Pair Skew Test Setup 3Tests Also same setup is used for MHL

MHL 2.1 Compliance Software for Automated Tx Tests: Option MHD MHL Customer Presentation

Tektronix MHL Solution Setup: Simple and Easy Sink and Dongle Min/Max Testing -2 Setup based on Direct Synthesis Capability of AWG7122C Series Test S

Tektronix MHL Protocol Analyzer 78

MIPI标准概述 移动终端方框图实例 显示单元 CMOS 图像传感器 RF IC (WCDMA, GSM, WLAN, FM, 蓝牙, GPS, MobileTV, 等等) 摄像机 驱动器IC 显示 驱动器IC 扬声器 耳机 音频 驱动器IC FM无线电 麦克风 DigRF 基带IC

Embedded Applications SATA BGA Today, SATA is expanding in specialized low power, compact and high performance areas with BGA and SATA-Express Solutio

D-PHY Tx测试解决方案 – 续  示波器 – 推荐: DPO7354或DPO/DSA/MSO70404/B – 用来测量规范+/-5%误差范围内的上升时间(150ps) – 如果不考虑上升时间的测试，可以使用DPO7254  探头 – 探头考虑因素 – 同时测量单端性能和差分性能 – 动态

New Opt.D-PHYTX  Opt.D-PHYTX : D-PHY Automated Solution – TekExpress option for Fully-Automated testing – Automation similar to Opt.USB-TX – Provide

D-PHY Rx : Test Solution Overview Simple, Quick, Easy and Re-usable  100% Coverage to Rx CTS – Meets all the requirements in UNH-IOL CTS document (v0

D-PHY Decode: Opt.SR-DPHY for DSI/ CSI-2 Decode Simultaneous Acquisition  Probe using Analog, Digital or Mixed Channels  Simultaneous probing of DSI

Memory Technology – Quick Overview  DRAM - dominant memory technology – Computer system memory – Server, desktop, laptop – Dynamic, volatile memory,

Step #1 Step #2 Automated Test Setup Select DDR Generation Select DDR Rate Choose measurements (Read / Write / CLK / Addr & Command)

2013/11/6 Tektronix Innovation Forum 2010 86 Effective Reporting / Archiving

Installation Process Memory Chip

BGA Chip Interposer for Oscilloscopes  Available in socket and solder-in versions – Socket design allows for multiple chip exchanges – Solder-in best

Visual Trigger and Serial Decode  Next generation designs have less margin and additional analysis must be done to pinpoint in on pattern dependent

PCB PCIe Conn. PCIe/SATA Conn. PCB Accept only a x2 PCIe, or a x1 PCIe cable Keys that reject the SATA cables Accept a x2 PCIe, or a x1 PCIe, or two

Triggering Techniques for Debugging DRAM Tektronix Confidential 90  Challenge: Dual-Rank System  Need to Isolate & Measure a Single Rank  Diffi

Triggering Techniques for Debugging DRAM Tektronix Confidential 91  ‘Visual’ Trigger Used to Qualify One Rank  Visual area (“keep-out” region) used

2013/11/6 92 High-Speed Serial Data Test Solutions… Design Verification Compliance Test Interconnect Test Interconnect Tx + - + - + - + - Rx Transmi