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Tektronix Technology Innovation Forum Spring 2012 High performance Storage Update

Agenda: High performance storage systems technology

update and introduction to 12G physical layer validation

 Introduction

– Industry Timeline

– SATA 3.1 Spec Revisions

– UTD 1.4.3 overview

– SATA/PCIE: SATAExpress Convergence

– SAS 3.0 r0 Spec Introduction and Measurement Considerations at ~12G

– 12+ G Design Problem

– Crosstalk

– BUJ

– WDP

– Signal Amplitude

– Instrumentation

REFERENCES

(1) Richard Mellitz: Intel: T10/ 11-275r0 SAS-3 12Gbs Transmitter Device Test Proposal

(2) Doron Lapidot: Tyco: T10/10-219r0 SAS 3.0 B-t-B Connector & Cable assembly Channel Performance @ 12Gbps “Modeling, Measurements & Simulations for BER compliance with multi

Aggressor System Interconnect”

(3) Mickey Felton: EMC: T10/11-239r0 Channel compliance points and lengths

(4) Kevin Witt: Maxim: T10/11-221r4 SAS-3 Electrical Spec (Draft)

(5) Mathieu Gagnon : PMC-SIERRA: T10/11-008r3 SAS-PHY: SAS3_EYEOPENING update

(6) Mladen Luksic: SATA-IO: IW12 Roadmap Update

General REFERENCES:

[1] IEEE is 25Gb/s on-board signaling Viable? KAM et al.: IEEE Transactions on advanced Packaging, Vol. 32, No. 2, May 2009.

[2] IEEE CMOS SerDes core with feed-forward and decision-feedback equalization . T. Beukem et al.: IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633–2645

[3] Alcatel-Lucent: DSP & FEC: Towards the Shannon Limit Timo Pfau ECOC’09 | WS1: DSP & FEC | Sept. 20, 2009

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