Agilent Technologies, Inc.
Agilent Technologies, Inc. 70 SATA PHY, TSG & OOB Test MOI v.1.1 Revision 1.4
Purpose: To provide verification that the measurement instrument meets the Lab Load requirement of the SATA
spec.
References: [1] Serial ATA Revision 3.0, 7.2.2.4 Lab Load Details
[2] SATA Interoperability Program Unified Test Document
Last Modification: March 25, 2009 (Revision 1.02)
Discussion:
C.1 - Introduction
The Serial ATA Revision 3.0 specifies a requirement for the ‘Lab Load’, which is defined in [1] as the
fixture (not including the SATA connector), cables, DC blocks, and the 50 ohm terminations inside of the HBWS.
Measurement of the setup as specified requires destructive modification to the SATA test fixture, which would not
be representative of interoperability conditions during conformance testing described in [2]. Therefore, a reasonable
approximation to this measurement is to verify the return loss of the instrument, cables and DC blocks used to
perform the measurement (as this is the dominant source of potential reflections due to impedance mismatch,
provided high-quality cables and components are used.)
In this measurement, the return loss of an Agilent DSA91204A Real-Time DSO was measured, using an
Agilent 86100C DCA-J Digital Communications Analyzer with a 54754A 18GHz Differential TDR module. The
DSO was set to 50mv/div vertical resolution, and was actively sampling at 40GS/s during the measurement. The
86100C was set to measure from DC to 20GHz. For documentation and verification purposes, two separate
calibrations were made and two separate measurements performed to validate both the S11 and S22 single-ended
return loss of Channels 1 and 3 of the DSO81304B, as well as the SDD11 differential return loss of the same
channels, respectively. This is done to provide full coverage of any interpretation of the lab load requirement as
stated in [1], either single-ended or differential. The results of both measurement studies are provided in C.2 below.
The setup for the 86100C and 54754A includes a full frame and module calibration using standard SMA
shorts and loads. The vertical scale for channels 1 and 2 is set to 100mV/div and the timebase set to 2.00ns/div, to
ensure that the entire length of the laboratory load is included in the TDR pulse response on the 86100C. The TDR
stimulus edge rate is set to 35ps. Option 202 Enhanced Impedance and S-Parameters measurement software
provides the conversion between the time-domain TDR response and the frequency domain return loss plots. Note:
for single-ended return loss measurements, the TDR Stimulus Mode is set to Single-Ended (see Figure C.1a); for
differential return loss measurements, the TDR Stimulus Mode is set to Differential (see Figure C.1b).
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